1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to methods for forming field effect transistors (FETs) and related devices.
2. Description of Related Art
Conventional methods of forming semiconductor devices, such as field effect transistors (FETs), may include the steps of forming a device isolation layer in predetermined regions of a semiconductor substrate to define transistor active regions, and forming gate electrodes crossing over the active regions. For example, in forming the device isolation layer, a trench mask pattern may be formed on the substrate. Using the trench mask pattern as an etch mask, the semiconductor substrate may be anisotropically etched to define a transistor active region having trenches on either side. The device isolation layer may be formed in the trenches on each side of the active region. Such a technique is known as shallow trench isolation (STI). In forming the gate electrode, a gate insulating layer and a gate conductive layer may be sequentially formed on the active region. The gate conductive layer may be patterned to form the gate electrode on the active region.
Non-volatile memory devices, such as flash memory devices, may further include a floating gate electrode positioned below the gate electrode. Forming the floating gate electrode may include two patterning steps using different mask patterns, which may be oriented horizontally and/or vertically with respect to the active region. A vertical patterning step may be similar to a step used for forming the gate electrode. However, a horizontal patterning step may require additional photolithographic steps and/or may involve precise photolithographic parameters, such as for an overlay.
With increasing demand for higher device integration density, it may be more difficult to achieve such precise photolithographic parameters. Accordingly, alternative patterning methods have been developed. For example, the floating gate conductive layer may be patterned using self-aligning methods.
Conventional methods for patterning a floating gate conductive layer will now be described with reference to FIG. 1 through FIG. 4.
As illustrated in FIG. 1, a pad oxide layer 20 is formed on a semiconductor substrate 10. The pad oxide layer 20 may be formed of silicon oxide. Trench mask patterns 30 are formed on a predetermined region of the pad oxide layer 20. Using the trench mask patterns 30 as etch masks, the pad oxide layer 20 and the substrate 10 are anisotropically etched to form trenches 15 around the trench mask patterns 30. The trenches 15 define active regions of the substrate 10 where an inversion layer channel may be formed. A thermal oxide layer 42 may be formed on sidewalls of the trenches 15, and a nitride liner 44 may be formed on the thermal oxide layer 42.
The trench 15 may be formed to a depth of about 2,000 to about 4,000 angstroms (Å). The trench mask pattern 30 may be made of a material such as silicon nitride that is etch-resistant with respect to the etchant used to form the trench 15. However, during the etching process, top and lateral surfaces of the trench mask pattern 30 may be partially etched, and as a result, sidewalls of the trench mask pattern 30 may be formed at an incline. In other words, etching may be greater at upper portions of the sidewalls of the trench mask pattern 30 than at lower portions thereof, such that upper portions of the trench mask pattern 30 may be narrower than lower portions. As such, the trench mask pattern 30 has inclined sidewalls. More particularly, an inclination angle θ1 of a sidewall of the trench mask pattern 30 is less than 90 degrees.
A device isolation layer is formed on the trench mask pattern 30 and in the trench 15. The device isolation layer is then planarized until a top surface of the trench mask pattern 30 is exposed to form a device isolation layer 46 that fills the trench 15. The device isolation layer 46 may be formed of silicon oxide.
Referring to FIG. 2, the trench mask pattern 30 is removed to expose the pad oxide layer 20. The trench mask pattern 30 may be removed in a manner that minimizes etching of the device isolation layer 46. The pad oxide layer 20 is removed to expose the active region of the substrate 10. As such, a trench is formed with opposing sidewalls defined by the device isolation layer 46 and a bottom surface defined by the active region of the substrate 10. The device isolation layer 46 also has inclined sidewalls. A gate insulating layer 50 is then formed on the exposed active region.
During removal of the pad oxide layer 20, the device isolation layer 46 may also be etched. In order to reduce etching damage at the active region of the substrate 10, removal of the pad oxide layer 20 may be performed using anisotropic etching. As a result, the sidewalls of the device isolation layer 46 remain at an incline. However, a sidewall inclination angle θ2 of the device isolation layer 46 may be different than the sidewall inclination angle θ1 of the trench mask pattern 30.
As illustrated in FIG. 3 and FIG. 4, a first conductive layer 60 is formed on the gate insulation layer 50 and the device isolation layer 46. The first conductive layer 60 may be formed using chemical vapor deposition (CVD). The first conductive layer 60 is then planarized until a top surface of the device isolation layer 46 is exposed to form a first conductive pattern 65 that is self-aligned between the inclined sidewalls of the device isolation layer 46.
In the event that a layer of a predetermined material, such as the first conductive layer 60, is deposited on a structure having a predetermined gap area, such as the trench defined by the device isolation layer 46 and the active region of the substrate 10, voids 88 may be formed due to poor step coverage. This is discussed, for example, in “Silicon Processing for the VLSI era: Volume 1—Process Technology” (1990, Lattice Press) by Stanley Wolf, p. 185, and “Silicon Processing for the VLSI era: Volume 2—Process Integration” (1990, Lattice Press) by Stanley Wolf, p. 202. More particularly, where the device isolation layer 46 has a sidewall inclination angle that is smaller than a right angle (i.e. θ2<90°), a sidewall of the first conductive layer 60 formed on the device isolation layer 46 may have an even smaller inclination angle θ3. This may result in an over-hang, as illustrated in FIG. 3. As such, the formation of voids 88 may be more likely. The voids 88 may contribute to device failures, as well as non-uniform device characteristics.